Single port and dual port static random access memory (SRAM) devices are known in the art. Dual port SRAMs utilize two addressing systems which allow read and write operations to occur independently within the SRAM. Thus, a read operation may be performed from one address at the same time that a write operation is performed to another address. Since these read and write operations occur independently, separate read and write clocks may be utilized. These separate read and write clocks can have different frequencies, thereby allowing the dual port SRAM to act as a buffer between two systems operating at different frequencies. For example, a conventional dual port SRAM can transfer data between one system and another system at a frequency of 80 Mhz.
One disadvantage of the dual port SRAM is that the dual addressing system necessitates a large memory cell. The memory cell size of a dual port SRAM is at least twice the memory cell size of a single port SRAM having the same capacity.
While single port SRAMs use less real estate on a chip, they use a single address system. Thus, only one memory cell may be accessed at any given time. Consequently, a single port SRAM is much slower than a dual port SRAM. In addition, single port SRAMs are limited to operation from a single clock signal. This clock signal must be used to control both the read and write operations. Thus, a single port SRAM, by itself, cannot be used to buffer the transfer of data between two systems operating at different frequencies.
Furthermore, it is known that an asynchronously operating dual port SRAM is capable of retransmitting data values stored in the SRAM. During such a retransmit operation, the dual port SRAM is instructed (typically by an external system) to read out data values previously stored in the dual port SRAM, starting at an initial address. During a retransmit operation, data values which were previously read out of the dual port SRAM may again be read out of the SRAM. Such a retransmit operation is allowed because of the independent nature of the read and write operations within the dual port SRAM.
It would therefore be advantageous to have a FIFO memory device which can control read and write operations with two separate clock signals, operate with the high speed data transfer characteristics of a dual port SRAM, exhibit the reduced layout area of a single port SRAM and be capable of performing a retransmit operation.